1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and method of reducing read disturbance in the same and, more particularly to a multi-valued nonvolatile semiconductor memory device where data of at least three values is recorded in a memory cell.
2. Description of the Related Art
A semiconductor nonvolatile memory device such as an EPROM and flash memory usually adopts a binary type memory cell structure where data taking either of two values of "0" and "1" is recorded in one memory cell transistor.
However, accompanied with the recent demand for increased capacity of nonvolatile semiconductor memory devices, a so-called multi-valued nonvolatile semiconductor memory device where data of three or more values is recorded in one memory cell transistor has been proposed (refer to for example "A Multi-Level 32-Mb Flash Memory", 95 ISSCC p. 132 on).
FIG. 1 is a view of the relationship between a threshold voltage Vth level and data contents (distribution) where data consisting of two bits and taking four values is recorded in one memory transistor in a NAND type flash memory.
In FIG. 1, the ordinate represents the threshold voltage Vth of the memory transistor, and the abscissa represents the frequency of distribution of the threshold values of the memory transistor, respectively.
The content of the 2-bit data comprising the data to be recorded in one memory transistor is represented by D2, D1!. There are four states, i.e., D2, D1!=1, 1!, 1, 0!, 0, 1!, and 0, 0!. Namely, there are four states of the data "0", data "1", data "2", and data "3".
Where there are four values, the distribution of the threshold voltages (distribution of the multi-valued data) becomes three voltages on the positive side and one on the negative side as shown in FIG. 1.
FIG. 2 is a view of the relationship of the threshold voltage Vth level and the data contents (distribution) where data consisting of 2 bits and taking four values is recorded in one memory transistor in a NOR type flash memory.
In FIG. 2, the ordinate represents the threshold voltage Vth of the memory transistor, and the abscissa represents the frequency of distribution of the threshold values of the memory transistor, respectively.
The content of the 2-bit data comprising the data to be recorded in one memory transistor is represented by D2, D1! similar to the above NAND type. There are also four states, i.e., D2, D1!=0, 0!, 0, 1!, 1, 0!, and 1, 1!.
In this NOR type, the distribution of the threshold voltages (distribution of the multi-valued data) becomes four voltages on the positive side as shown in FIG. 2.
In a NAND type or DINOR (divided NOR) type flash memory, the rewriting and reading of data are carried out in units of pages.
In the case of a general NAND type flash memory, in order to program memory cell transistors to a first program state (data "2"), a second program state (data "1"), and a third program state (data "0") from an erasing state (data "3"), writing is carried on the cells to have the write data 1, 0!, 0, 1!, and 0, 0! in a state where the voltage of the word line (gate voltage V.sub.G) is set to a constant voltage, for example, -10V. More specifically, the writing is carried out by setting, for example, the bit line voltage (drain voltage V.sub.D) to 6V (gate voltage V.sub.G =-10V) so the threshold voltage Vth is shifted to the distribution "10". At this time, a drain voltage V.sub.D =0V (gate voltage V.sub.G =-10V) is added to the cells to have the write data of 1, 1!, but since the electric field is insufficient, the threshold Vth does not change (the distribution "11" is maintained).
Next, the writing is carried out with respect to the cells to have the write data of 0, 1! and 0, 0!. Then, finally, the writing is carried out with respect to the cells to have the write data of 0, 0!, thereby ending the multi-valued writing. Note that, the writing operation is carried out by the write verify system.
At the time of reading, in the case of a NAND type, for example, the voltage of a selected word line is set to V.sub.WL00 for the reading, then it is set to V.sub.WL01 for the reading, and finally it is set to 0V for the reading. In this case, the voltage of the non-selected word lines is set to the positive side V.sub.pass (for example 5V).
In the case of a DINOR type, the voltage of the word line which is selected is set to V.sub.WL00 for the reading, then it is set to V.sub.WL01 for the reading, and finally it is set to V.sub.WL10 for the reading. In this case, the voltage of the non-selected word lines is set to 0V.
Then, the number of high level data in the read out data performed three times is counted, and the count (binary number) is defined as the data of On+1 (D2), IOn(D1).
In the case of a NAND type flash memory, the lowest voltage of the word lines at the time of reading is 0V, therefore when realizing a multi-valued structure, it is necessary to allocate 2.sup.n -1 distribution of threshold in the range from the upper limit of the distribution to 0V.
For this reason, there is a problem in that the width per distributions and the interval between distributions are narrow, so a high precision is required for the writing control and, at the same time, the memory is susceptible to disturbances and is weak in retention.
A more concrete explanation will be made of this problem below.
For example, in the case of four values, as the correspondence of the multi-valued data and the distribution of threshold values, as shown in FIG. 1, the data having a distribution of "10" is decided by 0V by setting the lower limit to 0.4V (for example, refer to 1996 IEEE International Solid-State Circuits Conference, ISSCC96/SESSION 2/FLASH MEMORY/PAPER TP 2.1: A 3.3 V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications, pp 32-33).
Further, due to the limitations of a NAND type flash memory, the upper limit of the threshold voltage Vth must be set to considerably lower than the voltage of the non-selected word lines so as to increase the amount of the cell current.
Further, the voltage of the non-selected word lines cannot be set too high due to the restrictions due to reading disturbances.
For this reason, it is necessary to arrange the distribution of three values in a range from 0V to 3.2V, so an extremely high precision control of the threshold voltage Vth becomes necessary. Further, also the disturbances and retention problems become serious.
In the case of a DINOR type flash memory, the distribution of the threshold voltage Vth becomes four voltages on the positive side as shown in FIG. 2. Since the voltage of the non-selected word lines is 0V, there is the problem that the width per distribution and the interval between distributions are narrow, so a high precision is required for the writing control and, at the same time, the memory is susceptible to disturbances and is poor in retention.